Z8FMC16100 Series Flash MCU
Product Specification
29
Short pulses on the Port pin can initiate Stop-Mode Recovery without initiating an in-
terrupt (if enabled for that pin).
Caution:
PWM Fault0 and Reset pin selection
The RESET pin can be set to function as a PWM Fault input. When selected, the RESET
input function is disabled. The FLTSELbit in the Reset Status and Control Register allows
software selection of the RESET pin function. The pin function is selected by writing the
the unlock sequence followed by the mode to this register. A software write to the FLTSEL
bit will override the value set by the FLTSELuser option bit
Reset Control Register Definitions
Writing the 14h, 92hunlock sequence to the Reset Status and Control Register address
unlocks access to the FLTSELbit. The locking mechanism prevents spurious writes to this
bit. The following sequence is required to unlock this register and write the FLTSELbit.
1. Write 14hto the Reset Status and Control Register (RSTSTAT).
2. Write 92hto the Reset Status and Control Register (RSTSTAT).
3. Write the FLTSELbit.
All steps of the unlock sequence must be written in the order listed.
Reset Status and Control Register
The Reset Status (RSTSTAT) Register, shown in Table 9, records the cause of the most
recent Reset or Stop-Mode Recovery. All status bits are updated on each Reset or Stop-
Mode Recovery event. Table 10 indicates the possible states of the Reset status bits fol-
lowing a Reset or Stop-Mode Recovery event. The RESET pin function is also select with
FLTSELbit.
PS024604-1005
P R E L I M I N A R Y
PWM Fault0 and Reset pin selection
ZILOG [ ZILOG, INC. ]
