Z8FMC16100 Series Flash MCU
Product Specification
201
To avoid disrupting a conversion already in progress, the STARTbit can be read to indicate
ADC operation status (busy or available).
Starting a new conversion while another conversion is in progress will stop the conver-
sion in progress and the new conversion will not complete.
Caution:
ADC Timing
Each ADC measurement consists of 3 phases:
1. Input sampling (programmable, minimum of 1.0µs)
2. Sample-and-hold amplifier settling (programmable, minimum of 0.5µs)
3. Conversion is 13 ADCLK cycles.
Figure 37 illustrates the control and flow of an ADC conversion.
Conversion period
Cleared by BUSY
START bit
Set by user
1.0 s sample period
SAMPLE/HOLD
Internal signal
Programmable
settling period
BUSY
Internal signal
13-clock
Conversion period
Figure 37. ADC Timing Diagram
PS024604-1005
P R E L I M I N A R Y
ADC Timing
ZILOG [ ZILOG, INC. ]
