Z8FMC16100 Series Flash MCU
Product Specification
xvii
List of Tables
Table 1. Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Pin Characteristics of the Z8FMC16100 Series Flash MCU . . . . . . . . . . . . . . . 11
Table 3. Z8FMC16100 Series Flash MCU Program Memory Maps. . . . . . . . . . . . . . . . 14
Table 4. Z8FMC16100 Series Information Area Map. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Register File Address Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Reset and Stop-Mode Recovery Characteristics and Latency . . . . . . . . . . . . . . 23
Table 7. System Reset Sources and Resulting Reset Action . . . . . . . . . . . . . . . . . . . . . . 24
Table 8. Stop-Mode Recovery Sources and Resulting Action. . . . . . . . . . . . . . . . . . . . . 28
Table 9. Reset Status and Control Register (RSTSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 10. Reset Status Register Values Following Reset. . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 11. Power Control Register 0(PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 13. Port Alternate Function Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 14. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 15. Port A–C GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Port Control Subregisters by Port Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Port A–C Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18. Port A–C Data Direction Sub-Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 19. Port A–B Alternate Function 0 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 20. Port A–C Output Control Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 21. Port A–C High Drive Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22. Port A–C STOP Mode Recovery Source Enable Sub-Registers . . . . . . . . . . . 45
Table 23. Port A–C Pull-Up Enable Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 24. Interrupt Edge Select Sub-Register (IRQES). . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. Interrupt Port Select Sub-Register (IRQPS). . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. Port A–B Alternate Function 1 Sub-Registers . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 27. Port A-C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 28. Port A-C Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 29. Reset, System Exception, and Interrupt Vectors in Order of Priority . . . . . . . 52
Table 30. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 31. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 32. IRQ0 Enable and Priority Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH). . . . . . . . . . . . . . . . . . . . . . . . . . 58
PS024604-1005
P R E L I M I N A R Y
List of Tables
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