Z8FMC16100 Series Flash MCU
Product Specification
xiv
Figure 29. Data Transfer Format—Master Write Transaction with a 10-Bit Address . 172
Figure 30. Data Transfer Format—Master Read Transaction with a 7-Bit Address . . . 174
Figure 31. Data Transfer Format—Master Read Transaction with a 10-Bit Address . . 175
Figure 32. Data Transfer Format—Slave Receive Transaction with 7-Bit Address . . . 179
Figure 33. Data Transfer Format—Slave Receive Transaction with 10-Bit Address . . 180
Figure 34. Data Transfer Format—Slave Transmit Transaction with 7-bit Address . . 181
Figure 35. Data Transfer Format—Slave Transmit Transaction with 10-Bit Address . 182
Figure 36. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 37. ADC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 38. ADC Convert Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 39. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 40. Recommended 20MHz Crystal Oscillator Configuration . . . . . . . . . . . . . . 237
Figure 41. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 42. Interfacing the On-Chip Debugger’s DBG Pin with
an RS-232 Interface (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 43. Interfacing the On-Chip Debugger’s DBG Pin with
an RS-232 Interface (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 44. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 45. Typical Active Mode IDD Versus System Clock Frequency . . . . . . . . . . . . 261
Figure 46. Maximum Active Mode IDD Versus System Clock Frequency . . . . . . . . . . 261
Figure 47. Typical Halt Mode IDD Versus System Clock Frequency . . . . . . . . . . . . . . 262
Figure 48. Maximum Halt Mode ICC Versus System Clock Frequency . . . . . . . . . . . . 262
Figure 49. Maximum Stop Mode IDD with VBO enabled versus Supply Voltage . . . . 263
Figure 50. Maximum Stop Mode IDD with VBO Disabled vs. Supply Voltage . . . . . . 264
Figure 51. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 52. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 53. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Figure 54. UART Timing with CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 55. UART Timing without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 56. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 57. Op Code Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
PS024604-1005
P R E L I M I N A R Y
List of Figures
ZILOG [ ZILOG, INC. ]
