Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
76
Reserved
These bits are reserved and must be 0.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-
isters (Tables 47 through 49) form the 24-bit reload value that is loaded into the Watch-
Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]. Writing to these registers sets the desired Reload Value. Read-
ing from these registers returns the current Watch-Dog Timer count value.
Caution:
The 24-bit WDT Reload Value must not be set to a value less than
000004Hor unpredictable behavior may result.
Table 47. Watch-Dog Timer Reload Upper Byte Register (WDTU)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTU
1
1
1
1
1
1
1
1
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
FF1H
ADDR
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTU—WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 48. Watch-Dog Timer Reload High Byte Register (WDTH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WDTH
1
1
1
1
1
1
1
1
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
FF2H
ADDR
R/W* - Read returns the current WDT count value. Write sets the desired Reload Value.
WDTH—WDT Reload High Byte
PS017610-0404
Watch-Dog Timer
ZILOG [ ZILOG, INC. ]
