Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
70
Timer 0-3 Control Registers
The Timer 0-3 Control (TxCTL) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
Table 44. Timer 0-3 Control Register (TxCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TEN
TPOL
PRES
TMODE
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F07H, F0FH, F17H, F1FH
ADDR
TEN—Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
One-Shot mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Continuous mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
Counter mode
When the timer is disabled, the Timer Output signal is set to the value of this bit.
When the timer is enabled, the Timer Output signal is complemented upon timer
Reload.
PWM mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the
Timer Output is forced High (1) upon PWM count match and forced Low (0) upon
Reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the
Timer Output is forced Low (0) upon PWM count match and forced High (1) upon
Reload.
PS017610-0404
Timers
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