Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
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this bit to 0 when a conversion has been completed.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already
in progress, the conversion restarts. This bit remains 1 until the conversion is complete.
Reserved
This bit is reserved and must be 0.
VREF
0 = Internal voltage reference generator enabled. The VREF pin should be left uncon-
nected (or capacitively coupled to analog ground).
1 = Internal voltage reference generator disabled. An external voltage reference must be
provided through the VREF pin.
CONT
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system
clock cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
ANAIN—Analog Input Select
These bits select the analog input for conversion. Not all Port pins in this list are available
in all packages for the Z8F640x family of products. Refer to the Signal and Pin Descrip-
tions chapter for information regarding the Port pins available with each package style.
Do not enable unavailable analog inputs.
0000 = ANA0
0001 = ANA1
0010 = ANA2
0011 = ANA3
0100 = ANA4
0101 = ANA5
0110 = ANA6
0111 = ANA7
1000 = ANA8
1001 = ANA9
1010 = ANA10
1011 = ANA11
11XX = Reserved.
PS017610-0404
Analog-to-Digital Converter
ZILOG [ ZILOG, INC. ]
