Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
68
set to 2-byte transfers, the temporary holding register for the Timer Reload High Byte is
not bypassed.
Table 40. Timer 0-3 Reload High Byte Register (TxRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F02H, F0AH, F12H, F1AH
ADDR
Table 41. Timer 0-3 Reload Low Byte Register (TxRL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TRL
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F03H, F0BH, F13H, F1BH
ADDR
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit Reload value, {TRH[7:0], TRL[7:0]}. This value is used
to set the maximum count value which initiates a timer reload to 0001H. In Compare
mode, these two byte form the 16-bit Compare value.
PS017610-0404
Timers
ZILOG [ ZILOG, INC. ]
