Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
67
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Table 38. Timer 0-3 High Byte Register (TxH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F00H, F08H, F10H, F18H
ADDR
Table 39>. Timer 0-3 Low Byte Register (TxL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TL
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F01H, F09H, F11H, F19H
ADDR
TH and TL—Timer High and Low Bytes
These 2 bytes, {TMRH[7:0], TMRL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0-3 Reload High and Low Byte (TxRH and TxRL) registers (Tables 40 and 41)
store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer Reload
High Byte register are stored in a temporary holding register. When a write to the Timer
Reload Low Byte register occurs, the temporary holding register value is written to the
Timer High Byte register. This operation allows simultaneous updates of the 16-bit Timer
Reload value.
In Compare mode, the Timer Reload High and Low Byte registers store the 16-bit Com-
pare value.
In single-byte DMA transactions to the Timer Reload High Byte register, the temporary
holding register is bypassed and the value is written directly to the register. If the DMA is
PS017610-0404
Timers
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