Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
180
SPI Slave Mode Timing
Figure 97 and Table 111 provide timing information for the SPI slave mode pins. Timing
is shown with SCK rising edge used to source MISO output data, SCK falling edge used to
sample MOSI input data.
SCK
T1
MISO
(Output)
Output Data
T2
T3
MOSI
Input Data
(Input)
T4
SS
(Input)
Figure 97. SPI Slave Mode Timing
Table 111. SPI Slave Mode Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
T1
SCK (transmit edge) to MISO output Valid Delay
2 * Xin
period
3 * Xin
period + 20
nsec
T2
T3
MOSI input to SCK (receive edge) Setup Time
MOSI input to SCK (receive edge) Hold Time
0
3 * Xin
period
T4
SS input assertion to SCK setup
1 * Xin
period
PS017610-0404
Electrical Characteristics
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