Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
176
General Purpose I/O Port Input Data Sample Timing
Figure 93 illustrates timing of the GPIO Port input sampling. The input value on a GPIO
Port pin is sampled on the rising edge of the system clock. The Port value is then available
to the eZ8 CPU on the second rising clock edge following the change of the Port value.
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
0 Value May Be Read
Register Latch
From Port Input
Data Register
Figure 93. Port Input Sample Timing
Table 107. GPIO Port Input Timing
Delay (ns)
Minimum Maximum
Parameter Abbreviation
TS_PORT
TH_PORT
TSMR
Port Input Transition to XIN Rise Setup Time
(Not pictured)
5
–
XIN Rise to Port Input Transition Hold Time
(Not pictured)
5
–
GPIO Port Pin Pulse Width to Insure Stop Mode Recovery
(for GPIO Port Pins enabled as SMR sources)
1µs
PS017610-0404
Electrical Characteristics
ZILOG [ ZILOG, INC. ]
