Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
126
When the DMA is configured for two-byte word transfers, the DMAx I/O Address register
must contain an even numbered address.
Table 72. DMAx I/O Address Register (DMAxIO)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_IO
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FB1H, FB9H
ADDR
DMA_IO—DMA on-chip peripheral control register address
This byte sets the low byte of the on-chip peripheral control register address on Register
File Page FH(addresses F00Hto FFFH).
DMAx Address High Nibble Register
The DMAx Address High register specifies the upper four bits of address for the Start/
Current and End Addresses of DMAx.
Table 73. DMAx Address High Nibble Register (DMAxH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DMA_END_H
DMA_START_H
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FB2H, FHAH
ADDR
DMA_END_H—DMAx End Address High Nibble
These bits, used with the DMAx End Address Low register, form a 12-bit End Address.
The full 12-bit address is given by {DMA_END_H[3:0], DMA_END[7:0]}.
DMA_START_H—DMAx Start/Current Address High Nibble
These bits, used with the DMAx Start/Current Address Low register, form a 12-bit Start/
Current Address. The full 12-bit address is given by {DMA_START_H[3:0],
DMA_START[7:0]}.
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
