Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
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Direct Memory Access Controller
Overview
The Z8F640x family device’s Direct Memory Access (DMA) Controller provides three
independent Direct Memory Access channels. Two of the channels (DMA0 and DMA1)
transfer data between the on-chip peripherals and the Register File. The third channel
(DMA_ADC) controls the Analog-to-Digital Converter (ADC) operation and transfers the
Single-Shot mode ADC output data to the Register File.
Operation
DMA0 and DMA1 Operation
DMA0 and DMA1, referred to collectively as DMAx, transfer data either from the on-chip
peripheral control registers to the Register File, or from the Register File to the on-chip
peripheral control registers. The sequence of operations in a DMAx data transfer is:
1. DMAx trigger source requests a DMA data transfer.
2. DMAx requests control of the system bus (address and data) from the eZ8 CPU.
3. After the eZ8 CPU acknowledges the bus request, DMAx transfers either a single byte
or a two-byte word (depending upon configuration) and then returns system bus
control back to the eZ8 CPU.
4. If Current Address equals End Address:
–
–
DMAx reloads the original Start Address
If configured to generate an interrupt, DMAx sends an interrupt request to the
Interrupt Controller
–
If configured for single-pass operation, DMAx resets the DENbit in the DMAx
Control register to 0 and the DMA is disabled.
If Current Address does not equal End Address, the Current Address increments by 1
(single-byte transfer) or 2 (two-byte word transfer).
PS017610-0404
Direct Memory Access Controller
ZILOG [ ZILOG, INC. ]
