Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
91
0 = Disable Multiprocessor mode.
1 = Enable Multiprocessor mode.
MPE—Multiprocessor Enable
0 = The UART processes all received data bytes.
1 = The UART processes only data bytes in which the multiprocessor data bit (9th bit) is
set to 1.
MPBT—Multiprocessor Bit Transmitter
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
Reserved
These bits are reserved and must be 0.
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request. The associated DMA will still be notified that
received data is available.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through
the Infrared Encoder/Decoder.
UARTx Baud Rate High and Low Byte Registers
The UARTx Baud Rate High and Low Byte registers (Tables 56 and 57) combine to create
a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud
rate) of the UART.
Table 56. UARTx Baud Rate High Byte Register (UxBRH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
BRH
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F46H and F4EH
ADDR
PS017610-0404
UART
ZILOG [ ZILOG, INC. ]
