Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
89
Table 53. UARTx Status 1 Register (UxSTAT1)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
Reserved
MPRX
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
F44H and F4CH
ADDR
Reserved
These bits are reserved and must be 0.
MPRX—Multiprocessor Receive
This status bit is for the receiver and reflects the actual status of the last multiprocessor bit
received. Reading from the UART Data register resets this bit to 0.
UARTx Control 0 and Control 1 Registers
The UARTx Control 0 and Control 1 registers (Tables 54 and 55) configure the properties
of the UART’s transmit and receive operations. The UART Control registers must ben be
written while the UART is enabled.
Table 54. UARTx Control 0 Register (UxCTL0)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F42H and F4AH
ADDR
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSEbit. If the CTS signal is low and the CTSEbit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
PS017610-0404
UART
ZILOG [ ZILOG, INC. ]
