Z8 Encore! XP® F08xA Series
Product Specification
107
minus four baud rate clocks to plus eight baud rate clocks around the expected time of an
incoming pulse. If an incoming pulse is detected inside this window this process is
repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to the initial state
and waits for the next falling edge. As each falling edge is detected, the Endec clock
counter is reset, resynchronizing the Endec to the incoming signal, allowing the Endec to
tolerate jitter and baud rate errors in the incoming datastream. Resynchronizing the Endec
does not alter the operation of the UART, which ultimately receives the data. The UART is
only synchronized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control regis-
ters as defined beginning on page 84.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the
UART Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling
the GPIO Port alternate function for the corresponding pin.
Caution:
PS024705-0405
P R E L I M I N A R Y
Infrared Encoder/Decoder
ZILOG [ ZILOG, INC. ]
