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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Seriess  
Product Specification  
100  
MPBT—Multiprocessor Bit Transmit  
This bit is applicable only when MULTIPROCESSOR (9-bit) mode is enabled. The 9th bit  
is used by the receiving device to determine if the data byte contains address or data infor-  
mation.  
0 = Send a 0 in the multiprocessor bit location of the data stream (data byte).  
1 = Send a 1 in the multiprocessor bit location of the data stream (address byte).  
DEPOL—Driver Enable Polarity  
0 = DE signal is Active High.  
1 = DE signal is Active Low.  
BRGCTL—Baud Rate Control  
This bit causes an alternate UART behavior depending on the value of the REN bit in the  
UART Control 0 Register.  
When the UART receiver is not enabled (REN=0), this bit determines whether the Baud  
Rate Generator issues interrupts.  
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value  
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.  
Reads from the Baud Rate High and Low Byte registers return the current BRG count  
value.  
When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate  
Registers to return the BRG count value instead of the Reload Value.  
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.  
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count  
value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High  
Byte is read.  
RDAIRQ—Receive Data Interrupt Enable  
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-  
troller.  
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only  
receiver errors generate an interrupt request.  
IREN—Infrared Encoder/Decoder Enable  
0 = Infrared Encoder/Decoder is disabled. UART operates normally.  
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data through  
the Infrared Encoder/Decoder.  
UART Address Compare Register  
The UART Address Compare register stores the multi-node network address of the UART.  
When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes are  
compared to the value stored in the Address Compare register. Receive interrupts and  
RDA assertions only occur in the event of a match.  
PS024705-0405  
P R E L I M I N A R Y  
UART