Z8 Encore! XP® 4K Series
Product Specification
103
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 65. UART Status 1 Register (U0STAT1)
BITS
7
6
5
4
3
2
1
0
Reserved
NEWFRM
MPRX
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R
R
F44H
ADDR
Reserved—Must be 0.
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data register resets this bit to 0.
UART Control 0 and Control 1 Registers
The UART Control 0 (UxCTL0) and Control 1 (UxCTL1) registers (Tables 66 and 67)
configure the properties of the UART’s transmit and receive operations. The UART Con-
trol registers must not be written while the UART is enabled.
Table 66. UART Control 0 Register (U0CTL0)
BITS
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F42H
ADDR
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSEbit. If the CTS signal is low and the CTSEbit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
PS022815-0206
UART
ZILOG [ ZILOG, INC. ]
