Z8 Encore! XP® 4K Series
Product Specification
33
Architecture
Figure 7 illustrates a simplified block diagram of a GPIO port pin. In this figure, the abil-
ity to accommodate alternate functions and variable port current drive strength is not illus-
trated.
Port Input
Data Register
Schmitt Trigger
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 7.GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins can be used for general-purpose I/O and access to on-chip
peripheral functions such as the timers and serial communication devices. The Port A–D
Alternate Function sub-registers configure these pins for either General-Purpose I/O or
alternate function operation. When a pin is configured for alternate function, control of the
port pin direction (input/output) is passed from the Port A–D Data Direction registers to
the alternate function assigned to this pin. Table 15 on page 36 lists the alternate functions
possible with each port pin. For those pins with more one alternate function, the alternate
function is defined through Alternate Function Sets sub-registers AFS1 and AFS2.
The crystal oscillator functionality is not controlled by the GPIO block. When the crystal
oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1
is overridden. In that case, those pins function as input and output for the crystal oscillator.
PS022815-0206
General-Purpose I/O
ZILOG [ ZILOG, INC. ]
