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Z8F012APB020SC 参数 Datasheet PDF下载

Z8F012APB020SC图片预览
型号: Z8F012APB020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R 4K系列高性能8位微控制器 [Z8 Encore XP-R 4K Series High-Performance 8-Bit Microcontrollers]
分类和应用: 微控制器外围集成电路光电二极管时钟
文件页数/大小: 276 页 / 3422 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® 4K Series  
Product Specification  
30  
HALT Mode  
Executing the eZ8 CPU’s HALT instruction places the device into HALT mode. In HALT  
mode, the operating characteristics are:  
Primary oscillator is enabled and continues to operate.  
System clock is enabled and continues to operate.  
eZ8 CPU is stopped.  
Program counter (PC) stops incrementing.  
Watch-Dog Timer’s internal RC oscillator continues to operate.  
If enabled, the Watch-Dog Timer continues to operate.  
All other on-chip peripherals continue to operate, if enabled.  
The eZ8 CPU can be brought out of HALT mode by any of the following operations:  
Interrupt  
Watch-Dog Timer time-out (interrupt or reset)  
Power-On reset  
Voltage-Brown out reset  
External RESET pin assertion  
To minimize current in HALT mode, all GPIO pins that are configured as inputs must be  
driven to one of the supply rails (VCC or GND).  
Peripheral-Level Power Control  
In addition to the STOP and Halt modes, it is possible to disable each peripheral on each  
of the Z8 Encore! XP® 4K Series devices. Disabling a given peripheral minimizes its  
power consumption.  
Power Control Register Definitions  
Power Control Register 0  
Each bit of the following registers disables a peripheral block, either by gating its system  
clock input or by removing power from the block.  
The default state of the low-power operational amplifier (LPO) is OFF. To use the LPO,  
clear the LPO bit, turning it ON. Clearing this bit might interfere with normal ADC mea-  
PS022815-0206  
Low-Power Modes