Z8 Encore! XP® 4K Series
Product Specification
178
stops fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is
automatically set when a BRK instruction is decoded and Breakpoints are enabled. If the
Flash Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
device. It cannot be written to 0.
0 = The Z8 Encore! XP® 4K Series device is operating in NORMAL mode.
1 = The Z8 Encore! XP® 4K Series device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRKinstruction (opcode 00H). By default, Break-
points are disabled and the BRKinstruction behaves similar to an NOP instruction. If this
bit is 1, when a BRKinstruction is decoded, the DBGMODEbit of the OCDCTL register is
automatically set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (FFH) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved—Must be 0.
RST—Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
OCD Status Register
The OCD Status register reports status information about the current state of the debugger
and the system.
Table 110. OCD Status Register (OCDSTAT)
BITS
7
6
5
4
3
2
1
0
DBG
HALT
FRPENB
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
DBG—Debug Status
0 = NORMAL mode
1 = DEBUG mode
PS022815-0206
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
