Z8 Encore! XP® 4K Series
Product Specification
126
ADC Control/Status Register 1
The ADC Control/Status Register 1 (ADCCTL1) configures the input buffer stage,
enables the threshold interrupts and contains the status of both threshold triggers. It is also
used to select the voltage reference configuration.
Table 73. ADC Control/Status Register 1 (ADCCTL1)
7
6
5
4
3
2
1
0
BITS
REFSELH ALMHST ALMLST ALMHEN ALMLEN
BUFMODE[2:0]
FIELD
RESET
R/W
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F71H
ADDR
REFSELH—Voltage Reference Level Select High Bit; in conjunction with the Low bit
(REFSELL) in ADC Control Register 0, this determines the level of the internal voltage
reference; the following details the effects of {REFSELH, REFSELL}; this reference is
independent of the Comparator reference
00= Internal Reference Disabled, reference comes from external pin
01= Internal Reference set to 1.0 V
10= Internal Reference set to 2.0 V (default)
11= Reserved
ALMHST—Alarm High Status; this bit can only be set by hardware and must be written
with a 1 to clear
0= No alarm occurred.
1= A high threshold alarm occurred.
ALMLST—Alarm Low Status; this bit can only be set by hardware and must be written
with a 1 to clear
0= No alarm occurred.
1= A low threshold alarm occurred.
ALMHEN—Alarm High Enable
0= Alarm interrupt for high threshold is disabled. The alarm status bit remains set when
the alarm threshold is passed.
1= High threshold alarm interrupt is enabled.
ALMLEN—Alarm Low Enable
0= Alarm interrupt for low threshold is disabled. The alarm status bit remains set when the
alarm threshold is passed.
1= Low threshold alarm interrupt is enabled.
BUFMODE[2:0] - Input Buffer Mode Select
000 = Single-ended, unbuffered input
001 = Single-ended, buffered input with unity gain
PS022815-0206
Analog-to-Digital Converter
ZILOG [ ZILOG, INC. ]
