Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
allel I/O with or without handshake, and address/data bus
for interfacing external memory.
Power connections follow conventional descriptions be-
low:
Notes: All Signals with a preceding front slash, "/", are
active Low, for example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
Connection
Power
Circuit
Device
V
V
DD
CC
Ground
GND
V
SS
(E40 Only)
VCC
XTAL /AS /DS R//W /RESET
Output Input
GND
Machine Timing
&
Port 3
Instruction Control
RESET
WDT, POR
Counter/
Timers (2)
ALU
FLAGS
Interrupt
OTP
Control
Register
Pointer
Two Analog
Comparators
Program
Counter
Register File
Port 2
Port 0
Port 1
8
4
4
I/O
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
(Bit Programmable)
(E40 Only)
Figure 1. Z86E30/E31/E40 Functional Block Diagram
2
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
