Z86017/Z16017 PCMCIA Interface Solution
Product Specification
57
Table 34. Window 2 Control Register: Address 14h (Continued)
Bit Placement Bit Name Description
Bit 4
EN_PAC2_ADDR_COMP When this bit is set, use address compare logic, when it is
cleared, acknowledge all PCMCIA chip selects.
Bit 5
EN_PAC2_HCS
When this bit is set, HCS1 is used as an external chip
select; when it is cleared, HCS0 is used as an external chip
select. Also see Registers 02h and 03h.
Bits 7-6
Number of wait states (in Master Clock period) inserted on
the
EEPROM Register
Address: SELECT 15h
Name: Window 2 Start Address LSB
Type: Write/Read
Table 35. Window 2 Start Address LSB: Address 15h
Bit Placement Bit Name
Description
Bits 7-0
LSB starting address for Port 2.
Programming Internal Registers
PS012002-1201
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