Z86017/Z16017 PCMCIA Interface Solution
Product Specification
54
EEPROM Register
Address: SELECT 10h
Name: Window 1 Control Register
Type: Write/Read
Table 30. Window 1 Control Register: Address 10h
Bit Placement Bit Name
Description
Bit 0
Bit 1
Bit 2
DIS_PAC1
When this bit is set to 1, the Port 1 Address Control and
decoder are disabled.
EN_PAC1_MEM
EN_PAC1_16
When this bit is set to 1, Memory Mode decoder is
enabled. When cleared, I/O mode is enabled.
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When cleared, it is high byte to high byte and
low byte to low byte.
Bit 3
Bit 4
Bit 5
READ_PROTECT
Allows two cards at the same address to be read. When this
bit is set, it prevents the PCMCIA bus from going active.
EN_PAC1_ADDR_COMP When this bit is set, use address compare logic; when it is
cleared, acknowledge all PCMCIA chip selects.
EN_PAC1_HCS
When this bit is set, HCS1 is used as an external chip
select. When this bit is cleared, HCS0 is used as an
external chip select. Also see Registers 02h and 03h
(Table 14 and Table 19).
Bits 7-6
Number of wait states (in Master Clock periods) inserted
on the PCMCIA bus.
00 = 0xTpmclkin (no wait states)
01 = 3x Tpmclkin
10 = 5x Tpmclkin
11 = 7x Tpmclkin
PS012002-1201
Programming Internal Registers
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