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Z8018008VSC 参数 Datasheet PDF下载

Z8018008VSC图片预览
型号: Z8018008VSC
PDF下载: 下载PDF文件 查看货源
内容描述: 家庭MPU [Family MPU]
分类和应用:
文件页数/大小: 326 页 / 1089 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8018x Family  
MPU User Manual  
10  
RTS0. Request to Send 0 (Output, Active Low). This output is a  
programmable modem control signal for ASCI channel 0.  
RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals  
are the receive data to the ASCI channels.  
RXS. Clocked Serial Receive Data (Input, Active High). This line is the  
receiver data for the CSIO channel. RXS is multiplexed with the CTS1  
signal for ASCI channel 1.  
ST. Status (Output, Active High). This signal is used with the M1 and  
HALT output to decode the status of the CPU machine cycle. Table 1  
provides status summary.  
Table 1.  
ST  
Status Summary  
HALT M1 Operation  
0
1
1
0
0
1
1
1
1
X
0
0
0
0
1
1
0
1
CPU operation (1st Op Code fetch)  
CPU operation (2nd Op Code and 3rd Op Code fetch)  
2
CPU operation (MC except for Op Code fetch)  
1
DMA operation  
HALT mode  
SLEEP mode (including SYSTEM STOP mode)  
1. X = Don't care  
2. MC = Machine cycle  
TEND0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This  
output is asserted active during the last write cycle of a DMA operation. It  
is used to indicate the end of the block transfer. TEND0 in multiplexed  
with CKA1.  
TEST. Test (Output, not on DIP version). This pin is for test and must be  
left open.  
UM005001-ZMP0400  
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