Z8018x Family
MPU User Manual
223
Table 41. 8-Bit Load (Continued)
Flags
Addressing
Ind Reg RegI Imp Rel Bytes States Operation
7
6
4
2
1
0
Operation
Name
Mnemonics
Op Code
Immed Ext
S
Z
H
P/V
N
C
Load
8-Bit
Data
LD (IX + d),m 11 011 101
S
D
4
15
m® (IX + d)
·
·
·
·
·
·
M
00 110 110
<d>
LD (IY + d),m 11 111 101
S
D
4
15
m® (IY + d)
·
·
·
·
·
·
M
01 110 g
<d>
<m>
LD (HL),g
01 110 g
11 011 101
01 110 g
<d>
S
S
D
1
3
7
gr® (HL)
·
·
·
·
·
·
·
·
·
·
·
·
M
LD (IX + d),g
D
D
15
gr® (IX+d)
M
LD (IY + d),g
11 111 101
01 110 g
<d>
S
3
15
gr® (IY + d)
·
·
·
·
·
·
M
(1) In the case of R1 and Z Mask, interrupts are not sampled at the end of LD A, I or LD A,R.
Table 42. 16-Bit Load
Flags
Addressing
Immed Ext Ind Reg RegI Imp Rel Bytes States Operation
7
6
4
2
1
0
Operation
Name
Mnemonics
Op Code
S
Z
H
P/V N
C
Load
16-Bit
Data
LD ww,mn
00 ww0 001
<n>
S
D
3
9
mn® ww
·
·
·
·
·
·
·
·
R
<m>
LD IX,mn
11 011 101
00 100 001
<n>
S
D
4
12
mn® IX
·
·
·
·
R
<m>
UM005001-ZMP0400
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