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EZ80L92AZ020SC00TR 参数 Datasheet PDF下载

EZ80L92AZ020SC00TR图片预览
型号: EZ80L92AZ020SC00TR
PDF下载: 下载PDF文件 查看货源
内容描述: [IC MCU 8BIT ROMLESS 100LQFP]
分类和应用:
文件页数/大小: 238 页 / 1067 K
品牌: ZILOG [ ZILOG, INC. ]
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eZ80L92 MCU  
Product Specification  
1
Architectural Overview  
Zilog’s eZ80L92 MCU is a high-speed single-cycle instruction-fetch microcontroller with  
a maximum clock speed of 50 MHz. The eZ80L92 MCU is a member of eZ80Acclaim!®  
family of Flash microcontrollers. It operates in Z80® compatible addressing mode (64  
KB) or full 24-bit addressing mode (16 MB). The rich peripheral set of the eZ80L92 MCU  
makes it suitable for various applications including industrial control, embedded  
communication, and point-of-sale terminals.  
Features  
The features of eZ80L92 MCU include:  
Single-cycle instruction fetch, high-performance, pipelined eZ80® CPU core1  
Low power features including SLEEP mode, HALT mode, and selective peripheral  
power-down control  
Two Universal Asynchronous Receiver/Transmitter (UARTs) with independent baud  
rate generators  
Serial Peripheral Interface (SPI) with independent clock rate generator  
Inter-Integrated Circuit (I2C) with independent clock rate generator  
Infrared Data Association (IrDA)-compliant infrared encoder/decoder  
New DMA-like eZ80 instructions for efficient block data transfer  
Glueless external peripheral interface with 4 Chip Selects, individual Wait State  
generators, and an external WAIT input pin—supports Intel-style and Motorola-style  
buses Fixed-priority vectored interrupts (both internal and external) and interrupt  
controller  
Real-time clock with an on-chip 32 kHz oscillator, selectable 50/60 Hz input, and  
separate VDD pin for battery backup  
Six 16-bit Counter/Timers with prescalers and direct input/output drive  
Watchdog Timer (WDT)  
24 bits of General-Purpose Input/Output (GPIO)  
JTAG and ZDI debug interfaces  
100-pin LQFP package  
3.0 V to 3.6 V supply voltage with 5 V tolerant inputs  
1. For simplicity, the term eZ80 CPU is referred as CPU for the rest of this document.  
PS013014-0107  
Architectural Overview  
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