Applications Note AN36
Issue1 - JULY 2002
Figure 19
Failsafe dual fan system.
In Figure 19 the SPD pin on both fans is
arranged such that they run at half speed, or
perhaps a little faster with R6 and R3.
Consider Fan A, R1 and C1 integrate out the
FG frequency pulses such that Q1 is always
kept off. If a lock condition is then
encountered with the fan the Lock/FG pin will
go permanently high and switch on Q1. This
in turn will send a signal to Fan B such that it
will switch R2 to ground. With the value of R2
chosen such that the SPD voltage of Fan B is
<1V it will ensure Fan B is set to full speed to
compensate to the now stopped Fan A.
SPD Voltage Conversion
There may be situations where the SDP input
control voltage range will be incompatible
with the application requirements perhaps
because the motor is to be controlled from an
already defined and different voltage source.
Figure 20 provides a simple voltage range
conversion for a control signal where a higher
voltage represents a higher speed.
Conversely R4, C4, Q2 and R5 will ensure that
if Fan B stops Fan A will be set to full speed.
By careful selection of the values of R1/C1 and
R4/C4 it is possible to only partially take out
the FG speed pulses. This will make one fan
speed up should the other slow down
sufficiently but not actually stop. To remove
the need for C1 and C4 the ZXBM2002 variant
with the Lock only output can be used so the
FG pulses do not need to be removed.
Figure 20
SPD control voltage level conversion.
AN 36 - 12
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