MVTX2801
Data Sheet
10.6.60 QOSC40 - CREDIT_C5_G1
Serial Interface Address:h556
Bits [5:0]
Bits [7:6]:
•
•
W5 - Credit register. (Default 5'h8)
Reserved
10.6.61 QOSC41- CREDIT_C6_G1
Serial Interface Address:h557
Bits [5:0]
Bits [7:6]:
•
•
W6 - Credit register. (Default 5'h8)
Reserved
10.6.62 QOSC42- CREDIT_C7_G1
Serial Interface Address:h558
Bits [5:0]
Bits [7:6]:
•
•
W7 - Credit register. (Default 5'h10)
Reserved
QOSC3B through QOSC42 represents the set of WFQ parameters (see section 7.5) for Gigabit port 1. The
granularity of the numbers (bits [5:0]) is 1, and their sum must be 64. QOSC3B corresponds to W0, and QOSC42
corresponds to W7.
Classes WFQ Credit Port G2
10.6.63 QOSC43 - CREDIT_C0_G2
Serial Interface Address:h55A
Bits [5:0]:
Bits [7:6]:
•
•
W0 - Credit register for WFQ. (Default 6'h04)
Priority type. Define one of the four QoS mode of operation for port 2 (Default 2'00)
- 00: Option 1
- 01: Option 2
- 10: Option 3
- 11: Option 4
See table below:
Queue
P7
P6
P5
P4
P3
P2
P1
P0
Option 1 Bit [7:6] = 2'B00
Option 2 Bit [7:6] = 2'B01
Option 3 Bit [7:6] = 2'B10
Option 4 Bit [7:6] = 2'B11
Credit for WFQ - Bit [5:0]
DELAY BOUND
BE
BE
SP
DELAY BOUND
WFQ
SP
WFQ
W7
W6
W5
W4
W3
W2
W1
W0
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Zarlink Semiconductor Inc.
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