MT9196
Data Sheet
The D-Channel read register is not preset to any particular value on power-up (PWRST) or software reset (RST).
b. A microport write to Address 15hex will result in a byte of data being loaded which is composed of four di-
bits (designated by roman numerals I, II, III, IV). These di-bits are destined for the two D-Channel bits
transmitted during each of frames n+1, n+2, n+3, n+4. Referring to Fig.8a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is mapped to frame n+3 and di bit IV is mapped to frame
n+4.
If no new data is written to address 15hex, the current D-channel register contents will be continuously re-
transmitted. The D-Channel write register is preset to all ones on power-up (PWRST) or software reset (RST).
An interrupt output is provided (IRQ) to synchronize microprocessor access to the D-Channel register during valid
ST-BUS periods only. IRQ will occur every fourth (eighth in 8 kb/s mode) ST-BUS frame at the beginning of the third
(second in 8 kb/s mode) ST-BUS bit cell period. The interrupt will be removed following a microprocessor Read or
Write of Address 15 hex or upon encountering the following frames’s FP input, whichever occurs first. To ensure D-
Channel data integrity, microport read/write access to Address 15 hex must occur before the following frame pulse.
See Figure 8b for timing.
8 kb/s operation expands the interrupt to every eight frames and processes data one-bit-per-frame. D-Channel
register data is mapped according to Figure 8c.
IRQ
Microport Read/Write Access
FP
n-3
n-2
n-1
n
n+1
n+2
n+3
n+4*
DSTo/
DSTi
Di-bit Group
Receive
D-Channel
I
II
III
IV
D0
D1
D4
D2
D3
D5 D6
D7
No preset value
I
III
II
IV
Di-bit Group
Transmit
D0
D1 D2
D4
D3
D5 D6
D7
D-Channel
Power-up reset to 1111 1111
* note that frame n+4 is equivalent to frame n of the next cycle.
Figure 8a - D-Channel 16 kb/s Operation
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Zarlink Semiconductor Inc.
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