MT9196
Data Sheet
FP
C4i
C2
tir =500 nsec max
Rpullup= 10 k
Din
D0
D1
tif =500 nsec max
IRQ
8 kb/s operation
Reset coincident with
Read/Write of Address 15 Hex
16 kb/s operation
Microport Read/Write Access
or next FP, whichever occurs first
Figure 8b - IRQ Timing Diagram
FP
Microport Read/Write Access
IRQ
n+2
n+4
n+6
n-7
I
n-6
II
n-5
n-4
n-3
V
n-2
n-1
n
n+1
n+3
n+5
n+7
n+8
D-Channel
III
D2
IV
D3
VI
D5
VII
D6
VIII
D7
Di-bit Group
Receive
D-Channel
D0
D1
D4
I
D0
II
D1
III
D2
IV
D3
VI
D5
VII
D6
VIII
D7
V
D4
No preset value
Di-bit Group
Transmit
D-Channel
Power-up reset to 1111 1111
Figure 8c - D-Channel 8 kb/s Operation
CEn - C-Channel
Channel 1 conveys the control/status information for the layer 1 transceiver. C-Channel data is transferred MSB
first on the ST-BUS by IDPC. The full 64 kb/s bandwidth is available and is assigned according to which transceiver
is being used. Consult the data sheet for the selected transceiver for its C-Channel bit definitions and order of bit
transfer.
When CEN is high, data written to the C-Channel register (address 14h) is transmitted, most significant bit first, on
DSTo. On power-up reset (PWRST) or software reset (RST, address 0Fh) all C-Channel bits default to logic high.
Receive C-Channel data (DSTi) is always routed to the read register regardless of this control bit's logic state.
When low, data transmission is halted and this timeslot is tri-stated on DSTo.
B1-Channel and B2-Channel
Channels 2 and 3 are the B1 and B2 channels, respectively. B-channel PCM associated with the Digital Gain,
Filter/CODEC and transducer audio paths is selected on an independent basis for the transmit and receive paths.
For example, the transmit path may use the B1 channel while the receive path uses the B2 channel. Although not
normally required, this flexibility is allowed.
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
