Data Sheet
Mode 2 - Fast RAM Mode
Mode 2 operates as a high speed dual port RAM
interface to the ST-BUS. Only the two transmit
RAM’s, Tx0 and Tx1, and the receive RAM, Rx0 are
active in this mode (i.e., control registers and
interrupt registers are inactive).
The main feature of this mode is fast access to the
dual-port RAM’s. Fast access allows high-speed
controllers to use this device as a data interface to
T1 and CEPT digital links. Timing information is
shown in Figure 15.
Mode 2 can also support 24 channel and 32 channel
operation. The channel configuration is selected
using 24/32 pin. When 24/32=0 the device operates
in 24 channel mode and when 24/32=1, it operates in
32 channel mode.
The physical interface in this mode resembles that of
a simple RAM device. The signals used to read
and write the device are CS, OE, R/W. The pinout of
the STPA in this mode is shown in Figure 3. Address
decoding for Tx0, Tx1, Rx0 is shown in Table 6.
Contention can arise for access to the dual port
RAMS. The occurrence of this is minimized since
the ST-BUS serial-to-parallel and parallel-to-serial
converters require RAM access for only 1/32 of
a channel time (i.e., last half cycle of C4i for
each channel). For contention to occur the high
speed controller must access the same RAM
location as that of the ST-BUS. For a parallel read
operation this corresponds to the current ST-BUS
channel and for a write operation, the next ST-BUS
channel. Access contention in Mode 2 is arbitrated
with the BUSY signal. BUSY is intended to hold
off any parallel access cycle until it again goes
inactive. Figure 16 shows how the access is
arbitrated for accesses near the contention window.
Applications using high speed access can easily
avoid generating BUSY by co-ordinating channel
ADDRESS BITS
A
5
0
•
•
•
0
1
•
•
•
1
A
4
0
•
•
•
1
0
•
•
•
1
A
3
0
•
•
•
1
0
•
•
•
1
A
2
0
•
•
•
1
0
•
•
•
1
A
1
0
•
•
•
1
0
•
•
•
1
A
0
0
•
•
•
1
0
•
•
•
1
READ
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
Rx0 - Channel 0
•
•
•
Rx0 - Channel 31
MT8920B
reads and writes with framing and channel boundary
information.
Mode 3 - Parallel Bus Controller
In this mode the STPA outputs all necessary signals
required to drive devices attached to the parallel
port. The STPA can be used to drive devices such
as RAM’s, FIFO’s, latches, A/D and D/A converters,
and CODECS, directly from the ST-BUS without an
intervening
µP.
As with the other modes, Mode 3
can operate from 32 channels or 24 channels by
connecting 24/32 high or low, respectively. This
allows devices to be driven remotely via a T1 or
CEPT digital trunk link when used with Zarlink’s trunk
products.
Referring to Figure 1, the Address Generator block
generates and drives the external address lines
A4-A0. The STPA also generates OE (output
enable) and WE (write enable) to facilitate data
transfers from Rx0 RAM and to Tx0 RAM. Tx1 RAM
is unavailable in this mode.
The STPA, in Mode 3, generates external addresses
in a particular sequence that minimizes throughput
delay through the device. When channel N is
present on the ST-BUS, the STPA generates
address N+1 on the address bus and asserts OE
to output data from an external device and latch it
into the STPA. During the same channel N, the
STPA will generate address N-1 with WE asserted
to write from the STPA to an external device. Timing
for Mode 3 transfers is shown in Figure 17. All
parallel bus signals are synchronized to the ST- BUS
clock.
The device must be selected using CS in order for
the parallel bus drivers to be enabled. CS should
remain active for four ST-BUS bit periods (8 x C4i
cycles) since a read and a write operation require 2
bit periods each. The STPA generates a signal STCH
(start of channel) which becomes active at the start
of each channel and remains active for 1/2 of the
channel time (Figure 18). This signal may be
REGISTERS
WRITE
Tx0 - Channel 0
•
•
•
Tx0 - Channel 31
Tx1 - Channel 0
•
•
•
Tx1 - Channel 31
Table 6. Mode 2 Address Map
11
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
