MT88L70
Data Sheet
IN+
IN-
GS
VRef
INH
PWDN
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE
IN+
IN-
GS
VRef
INH
PWDN
NC
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
StD
NC
Q4
Q3
Q2
Q1
TOE
18 PIN PDIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
18
1
2
3
4
5
6
7
8
9
10
11-
14
15
20
1
2
3
4
5
6
8
9
10
11
12-
15
17
Name
IN+
IN-
GS
V
Ref
INH
Non-Inverting Op-Amp (Input).
Inverting Op-Amp (Input).
Gain Select.
Gives access to output of front end differential amplifier for connection of
feedback resistor.
Reference Voltage (Output).
Nominally V
DD
/2 is used to bias inputs at mid-rail (see Figure 5
and Figure 6).
Inhibit (Input).
Logic high inhibits the detection of tones representing characters A, B, C and
D. This pin input is internally pulled down.
Description
PWDN
Power Down (Input).
Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.
OSC1
OSC2
V
SS
TOE
Clock (Input).
Clock (Output).
A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.
Ground (Input).
0 V typical.
Three State Output Enable (Input).
Logic high enables the outputs Q1-Q4. This pin is pulled
up internally.
Q1-Q4
Three State Data (Output).
When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.
StD
Delayed Steering (Output).Presents
a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V
TSt
.
Early Steering (Output).
Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to
a logic low.
16
18
ESt
2
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
