Advance Information
MT88E45
start
start
start
TIP/RING
b7
stop
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5
(A/B) WIRES
stop
stop
t
IDD
start
start
start
DATA
(Output)
b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3
stop
stop
stop
DCLK
(Output)
t
CL
t
t
1/f
DCLK0
CH
CRD
DR
(Output)
t
RL
Figure 13 - Serial Data Interface Timing (Mode 0)
Word N+1
3
Word N
7
Demodulated Data
(Internal Signal)
1
5
stop
0
2
4
6
7
stop
start
Note 1
t
RL
DR (Data Ready)
(Output)
Note 2
>t
>t
1/f
4
DDS
DDH
DCLK1
DCLK (Data Clock)
(Schmitt Input)
DATA
(Output)
7
stop
0
1
2
3
5
6
7
stop
0
Word N-1
Word N
The DCLK input must be low before and after DR falling edge.
Note 1: DCLK occurs during DR low and returns DR to high.
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.
Figure 14 - Serial Data Interface Timing (Mode 1)
21
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