MT88E43B
Data Sheet
Internal to the MT88E43, the demodulated data bits are sampled and stored. After the 8th bit, the word is parallel
loaded into an 8 bit shift register and DR goes low. The shift register’s contents are shifted out to the DATA pin on
the supplied DCLK’s rising edge in the order they were received.
If DCLK begins while DR is low, DR will return to high upon the first DCLK. This feature allows the associated
interrupt (see section on "Interrupt") to be cleared by the first read pulse. Otherwise DR is low for half a nominal bit
time (1/2400 sec).
After the last bit has been read, additional DCLKs are ignored.
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Carrier Detect
The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the
presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a
digital algorithm before the CD output is set low to indicate carrier detection. An 8ms hysteresis is provided to allow
for momentary signal drop out once CD has been activated. CD is released when there is no activity at the FSK
bandpass filter output for 8 ms.
When CD is inactive (high), the raw output of the demodulator is ignored by the data timing recovery circuit (refer to
Figure 1). In mode 0, the DATA pin is forced high. No DCLK or DR signal is generated. In mode 1, the internal shift
register is not updated. No DR is generated. If DCLK is clocked (in mode 1), DATA is undefined.
Note that signals such as dual tone alert signal, speech and DTMF tones also lie in the FSK frequency band and
the carrier detector may be activated by these signals. The signals will be demodulated and presented as data. To
avoid false data detection, the FSKen pin should be used to disable the FSK demodulator when no FSK signal is
expected.
Ringing, on the other hand, does not pose a problem as it is ignored by the carrier detector.
Interrupt
To facilitate interfacing with microcontrollers running interrupt driven firmwear, an open drain interrupt output INT is
provided. INT is asserted when TRIGout is low, StD is high, or DR is low. When INT is asserted, these signals
should be read (through an input port of the microcontroller) to determine the cause of the interrupt (TRIGout, StD
or DR) so that the appropriate response can be made.
When system power is first applied, TRIGout will be low because capacitor C3 at TRIGRC (see Figure 3) has no
initial charge. This will result in an interrupt upon power up. Also when system power is first applied and the PWDN
pin is low, an interrupt will occur due to StD. Since there is no charge across the capacitor at the St/GT pin in Figure
4, StD will be high triggering an interrupt. The interrupts will not clear until both capacitors are charged. The
microcontroller should ignore interrupt from these sources on initial power up until there is sufficient time to charge
the capacitors.
It is possible to clear StD and its interrupt by asserting PWDN immediately after system power up. When PWDN is
high, StD is low. PWDN will also force both ESt and the comparator output low, Q2 will turn on so that the capacitor
at the St/GT pin charges up quickly (refer to Figure 4).
Power Down Mode
For applications requiring reduced power consumption, the MT88E43 can be powered up only when it is required,
that is, upon detection of one of three CLIP/CID call arrival indicators: line reversal, ring burst and ringing.
The MT88E43 is powered down by asserting the PWDN pin. In powerdown mode, the crystal oscillator, opamp and
all internal circuitry, except for TRIGin, TRIGRC and TRIGout pins, are disabled. The three TRIG pins are not
affected by power down, such that, the MT88E43 can still react to call arrival indicators. The MT88E43 can be
powered up by grounding the PWDN pin.
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