MT88E43B
Item
Signal level
differential
(twist)
Unwanted
signals
Transmission
rate
Word format
BT
up to 6dB
Bellcore
up to 10dB
2
Data Sheet
<= -20dB
(300-3400Hz)
1200 baud
±±
1%
1 start bit (logic
0), 8 bit word
(LSB first), 1 to
10 stop bits
(logic 1)
<= -25dB
(0-4kHz)
3
1200 baud
±±
1%
1 start bit (logic
0), 8 bit word
(LSB first),
1 stop bit
(logic 1)
4
Table 2 - FSK Characteristics
1. The signal power is expressed in dBm referenced to 600
ohm at the CPE tip/ring (A/B) interface.
2. SR-3004,Issue 2, January 1995.
3. The frequency range is specified in GR-30-CORE.
4. Up to 20 marks may be inserted in specific places in a single
or multiple data message.
The FSK characteristics described in Table 2 are listed in BT and Bellcore specifications. The BT signal frequencies
correspond to CCITT V.23. The Bellcore frequencies correspond to Bell 202. The U.K.’s CCA requires that the TE
be able to receive both CCITT V.23 and Bell 202, as specified in the BT and Bellcore specifications. The MT88E43
is compatible with both formats without any adjustment.
•
3-wire User Interface
The MT88E43 provides a powerful dual mode 3-wire interface so that the 8-bit data words in the demodulated FSK
bit stream can be extracted without the need either for an external UART or for the TE/CPE’s microcontroller to
perform the UART function in software. The interface is specifically designed for the 1200 baud rate and is
comprised of the DATA, DCLK (data clock) and DR (data ready) pins. Two modes (modes 0 and 1) are selectable
via control of the device’s MODE pin: in mode 0, data transfer is initiated by the MT88E43; in mode 1, data transfer
is
initiated
by
the
external
microcontroller.
Mode 0
This mode is selected when the MODE pin is low. It is the MT8841 compatible mode where data transfer is initiated
by the device.
In this mode, the MT88E43 receives the FSK signal, demodulates it, and outputs the data directly to the DATA pin
(refer to Figure 14). For each received stop and start bit sequence, the MT88E43 outputs a fixed frequency clock
string of 8 pulses at the DCLK pin. Each clock rising edge occurs in the centre of each DATA bit cell. DCLK is not
generated for the stop and start bits. Consequently, DCLK will clock only valid data into a peripheral device such as
a serial to parallel shift register or a micro-controller. The MT88E43 also outputs an end of word pulse (data ready)
on the DR pin. The data ready signal indicates the reception of every 10-bit word (including start and stop bits) sent
from the network to the TE/CPE. This DR signal can be used to interrupt a micro-controller. DR can also cause a
serial to parallel converter to parallel load its data into a microcontroller. The mode 0 data pin can also be connected
to a personal computer’s serial communication port after converting from CMOS to RS-232 voltage levels.
Mode 1
This mode is selected when the MODE pin is high. In this mode, the microcontroller supplies read pulses (DCLK) to
shift the 8-bit data words out of the MT88E43, onto the DATA pin. The MT88E43 asserts DR to denote the word
boundary and indicate to the microprocessor that a new word has become available (refer to Figure 16).
10
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
