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MT88E43BS1 参数 Datasheet PDF下载

MT88E43BS1图片预览
型号: MT88E43BS1
PDF下载: 下载PDF文件 查看货源
内容描述: 扩展电压主叫号码识别电路2 [Extended Voltage Calling Number Identification Circuit 2]
分类和应用: 电信集成电路电信电路电话电路光电二极管
文件页数/大小: 29 页 / 560 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
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MT88E43B  
Data Sheet  
The U.K.’s CCA specification TW/P&E/312 proposes an alternate CDS TE interface. According to TW/P&E/312,  
data is transmitted after a single burst of ringing rather than before the first ringing cycle (as specified in the BT  
standards). The Idle State Tone Alert Signal is not required as it is replaced by a single ring burst. MT88E43 has the  
capability to detect the ring burst. It can also demodulate either Bell-202 or CCITT V.23 FSK data following the ring  
burst. The U.K.’s CCA specifies that data can be transmitted in either format.  
Bellcore specification GR-30-CORE is the generic requirement for transmitting asynchronous voiceband data to  
Customer Premises Equipment (CPE). Another Bellcore specification SR-TSV-002476 describes the same  
requirements from the CPE’s perspective. The data transmission technique specified in both documents is  
applicable in a variety of services like Calling Number Delivery (CND), Calling Name Delivery (CNAM) and Calling  
Identity Delivery on Call Waiting (CIDCW) - services promoted by Bellcore.  
In CND/CNAM service, information about a calling party is embedded in the silent interval between the first and  
second ring burst. The MT88E43 detects the first ring burst and can then be setup to receive and demodulate the  
incoming Bell-202 FSK data. The device will output the demodulated data onto a 3-wire serial interface.  
In CIDCW service, information about an incoming caller is sent to the subscriber, while he/she is engaged in  
another call. A CPE Alerting Signal (CAS) indicates the arrival of CIDCW information. The MT88E43 can detect the  
alert signal and then be setup to demodulate incoming FSK data containing CIDCW information.  
Functional Description  
Detection of CLIP/CID Call Arrival Indicators  
The circuit in Figure 3 illustrates the relationship between the TRIGin, TRIGRC and TRIGout signals. Typically, the  
three pin combination is used to detect an event indicated by an increase of the TRIGin voltage from VSS to above  
the Schmitt trigger high going threshold VT+ (see DC electrical characteristics).  
Figure 3 shows a circuit to detect any one of three CLIP/CID call arrival indicators: line reversal, ring burst and  
ringing.  
VDD  
C1=100nF  
MT88E43  
V3  
V1  
Tip/A  
R1=499K  
R2=499K  
max VT+ = 0.68 VDD  
min V = 0.48 VDD  
T+  
R3=200K  
TRIGin  
C2=100nF  
V2  
Ring/B  
V4  
is:  
To determine values for C3 and R5:  
R5C3=-t / ln(1-VTRIGRC/VDD  
)
Notes:  
The application circuit must ensure that,  
TRIGin>max V  
TRIGRC  
V
T+  
where max V =3.74V @V =5.5V.  
T+ DD  
Tolerance to noise between A/B and V  
SS  
max Vnoise = (min VT+)/0.30+0.7 =5.6Vrms @4.5V V  
DD  
where min VT+ = 2.16V @V =4.5V.  
DD  
Suggested R C component values:  
5
3
R5 from 10Kto 500KΩ  
C3 from 47nF to 0.68µF  
TRIGout  
To Microcontroller  
An example is C3=220nF, R5=150K; TRIGout low  
from 21.6ms to 37.6ms after TRIGin Signal stops  
triggering the circuit.  
Figure 3 - Circuit to Detect Line Reversal, Ring Burst and Ringing  
4
Zarlink Semiconductor Inc.  
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