MT88E43B
Data Sheet
start
stop
start
stop
start
stop
TIP/RING
(A/B)
b7
b6
b6
b0 b1 b2
1
0
b0 b1 b2 b3 b4 b5
b7
b6
b0 b1 b2 b3 b4 b5
b7
b6
1
0
1
0
WIRES
t
IDD
start
start
start
b7
b0 b1 b2 b3 b4 b5
b7
b0 b1 b2 b3 b4 b5
b7
DATA
b0 b1 b2
stop
stop
stop
1/fDCLK0
DCLK
DR
tRL
t
CRD
Figure 14 - Serial Data Interface Timing (MODE 0)
VHM
VLM
DCLK
t
R1
Figure 15 - DCLK Mode 1 Input Timing
word N+1
word N
7
Demodulated
internal bit
stream
stop
0
2
3
4
6
7
stop
start
1
5
tRL
DR
2
1
1/fDCLK1
tDDS
tDDH
DCLK
DATA
0
6
7
0
1
2
3
4
5
6
7
word N-1
1 DCLK clears DR
2 DCLK does not clear DR, so DR is low for maximum time (1/2 bit width)
word N
Figure 16 - Serial Data Interface Timing (Mode 1)
22
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
