MT8889C
Functional Description
Data Sheet
The MT8889C Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain
setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and
pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected.
The adaptive micro interface allows microcontrollers, such as the 68HC11, 80C51 and TMS370C50, to access the
MT8889C internal registers.
20 PIN PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
20
1
2
3
4
5
6
7
24
1
2
3
4
5
6
7
28
1
2
4
6
7
8
9
Name
IN+
IN-
GS
V
Ref
V
SS
OSC1
OSC2
Non-inverting
op-amp input.
Inverting
op-amp input.
Gain Select.
Gives access to output of front end differential amplifier for
connection of feedback resistor.
Reference Voltage
output (V
DD
/2).
Ground (0V).
DTMF clock/oscillator input. Connect a 4.7 M
Ω
resistor to VSS if crystal oscillator
is used.
Oscillator
output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven
externally.
Output from internal DTMF transmitter.
Chip Select
input. This signal must be qualified externally by either address
strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal,
see Figure 14.
Register Select
input. Refer to Table 3 for bit interpretation. TTL compatible.
Description
8
9
10
10
11
12
12
13
14
TONE
CS
R/W
(WR)
(Motorola)
Read/Write
or (Intel)
Write
microprocessor input. TTL compatible.
11
12
13
14
15
17
RS0
DS
(RD)
(Motorola)
Data Strobe
or (Intel)
Read
microprocessor input. Activity on this
input is only required when the device is being accessed. TTL compatible.
2
Zarlink Semiconductor Inc.
TONE
R/W/WR
CS
RSO
NC
DS/RD
IRQ/CP
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
NC
TONE
R/W/WR
CS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
12
13
14
15
16
17
18
NC
VRef
VSS
OSC1
OSC2
NC
NC
4
3
2
1
28
27
26
GS
NC
IN-
IN+
VDD
St/GT
EST
5
6
7
8
9
10
11
•
25
24
23
22
21
20
19
NC
NC
NC
D3
D2
D1
D0
28 PIN PLCC
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
