欢迎访问ic37.com |
会员登录 免费注册
发布采购

MT8889CN1 参数 Datasheet PDF下载

MT8889CN1图片预览
型号: MT8889CN1
PDF下载: 下载PDF文件 查看货源
内容描述: [DTMF Signaling Circuit, CMOS, PDSO24, 5.30 MM, LEAD FREE, MO-150AG, SSOP-24]
分类和应用: 电信光电二极管电信集成电路
文件页数/大小: 24 页 / 371 K
品牌: ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
 浏览型号MT8889CN1的Datasheet PDF文件第2页浏览型号MT8889CN1的Datasheet PDF文件第3页浏览型号MT8889CN1的Datasheet PDF文件第4页浏览型号MT8889CN1的Datasheet PDF文件第5页浏览型号MT8889CN1的Datasheet PDF文件第6页浏览型号MT8889CN1的Datasheet PDF文件第7页浏览型号MT8889CN1的Datasheet PDF文件第8页浏览型号MT8889CN1的Datasheet PDF文件第9页  
MT8889C
Integrated DTMF Transceiver
with Adaptive Micro Interface
Data Sheet
Features
Central office quality DTMF transmitter/receiver
Low power consumption
High speed adaptive micro interface
Adjustable guard time
Automatic tone burst mode
Call progress tone detection to -30 dBm
Ordering Information
MT8889CE
MT8889CS
MT8889CN
MT8889CE1
MT8889CS1
MT8889CN1
MT8889CSR
MT8889CSR1
*Pb
20 Pin PDIP
20 Pin SOIC
24 Pin SSOP
20 Pin PDIP*
20 Pin SOIC*
24 Pin SSOP*
20 Pin SOIC
20 Pin SOIC*
Free Matte Tin
Tubes
Tubes
Tubes
Tubes
Tubes
Tubes
Tape & Reel
Tape & Reel
July 2008
Applications
Credit card systems
Paging systems
Repeater systems/mobile radio
Interconnect dialers
Personal computers
-40°C to +85°C
Description
The MT8889C is a monolithic DTMF transceiver with
call progress filter. It is fabricated in CMOS technology
offering low power consumption and high reliability.
The receiver section is based upon the industry
standard MT8870 DTMF receiver while the transmitter
utilizes a switched capacitor D/A converter for low
distortion, high accuracy DTMF signalling. Internal
counters provide a burst mode such that tone bursts
can be transmitted with precise timing. A call progress
filter can be selected allowing a microprocessor to
analyze call progress tones.
The MT8889C utilizes an adaptive micro interface,
which allows the device to be connected to a number
of popular microcontrollers with minimal external logic.
TONE
D/A
Converters
Row and
Column
Counters
Transmit Data
Register
Status
Register
Control
Register
A
Control
Register
B
Data
Bus
Buffer
D0
D1
D2
D3
IRQ/CP
Tone Burst
Gating Cct.
IN+
IN-
GS
OSC1
OSC2
Oscillator
Circuit
Bias
Circuit
V
DD
V
Ref
V
SS
+
-
Dial
Tone
Filter
Control
Logic
Interrupt
Logic
High Group
Filter
Low Group
Filter
Control
Logic
Digital
Algorithm
and Code
Converter
DS/RD
I/O
Control
CS
R/W/WR
RS0
Steering
Logic
Receive Data
Register
ESt
St/GT
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.