MT352
Data Sheet
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the MT352 have been heavily optimized to minimize hardware and chip
area. This is proven by its 220 mW (typical) power consumption, which is the lowest of any OFDM device in the
market today.
1.1 Analogue-to-Digital Converter
The MT352 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:
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•
•
4.57 MHz near-zero IF
36.17 MHz IF
43.75 MHz IF
The ADC can be clocked using:
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Crystal oscillator with a 20.48 MHz crystal
4 MHz or 27 MHz clock input
An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The crystal
frequency of 20.48 MHz is used for 36.17 MHz IF sampling and 19.6267 MHz is used for 43.75 MHz IF sampling.
Note that this 19.6267 MHz sampling clock can be generated from the 20.48 MHz crystal by appropriately
programming the PLL. Hence the same 20.48 MHz crystal can support 6, 7 and 8 MHz OFDM as well as 36.17 and
43.75 MHz IF.
1.2 Automatic Gain Control
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error
signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which
has to be RC low-pass filtered to obtain the voltage to control the amplifier. Upper and lower limits can be set to the
AGC control voltage using registers.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC
clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined
assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit
theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This
reference or target value may have to be lowered slightly for some applications. Slope control bits have been
provided for the AGCs and these have to be set correctly depending on the Gain-versus-Voltage slope of the gain
control amplifiers.
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being
established. This is one of the features of MT352 used to minimize acquisition time. A robust AGC lock mechanism
is provided and the other parts of the MT352 begin to acquire only after the AGC has locked. Two AGC control
outputs are available, one to drive an RF amplifier and the other to control an IF amplifier. The parameters for both
loops are programmable. In the default mode, only the IF AGC loop is activated.
1.3 IF to Baseband Conversion
Sampling a 36.17 MHz IF signal at 20.48 MHz results in a spectrally inverted OFDM signal centred at 4.79 MHz.
Sampling a 43.75 MHz IF signal at 19.6267 MHz gives a non-inverted signal at 4.5 MHz. The first step of the
demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in baseband. A
correction for spectral inversion is implemented during this conversion process. Note also that the MT352 has
control mechanisms to search automatically for an unknown spectral inversion status.
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Zarlink Semiconductor Inc.
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