MT352
Data Sheet
1.0 Functional Description
A functional block diagram of the MT352 OFDM demodulator is shown in Figure 3. This accepts an IF analogue
signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and
frequency synchronization operations are all digital and there are no analogue control loops except the AGC. The
frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to
combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,
the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC
can be switched from one stream to another with minimal interruption to the transport stream.
Figure 3 - OFDM Demodulator Diagram
The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to
provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures
minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi
and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at
the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting
intervals of these are programmable over a very wide range.
Figure 4 - FEC Block Diagram
The FSM controller shown in Figure 3 above controls both the demodulator and the FEC. It also drives the 2-wire
bus to the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of
the received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This
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