MT352
Data Sheet
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the ENTEI bit in the CONFIG register (0x8A) is set high (default), the TEI bit of any uncorrectable
packet will automatically be set to '1'. If ENTEI bit is low then TEI bit will not be changed (but note that if this bit is
already 1, for example, due to a channel error which has not been corrected, it will remain high at output).
3.3.2 MPEG data output signals
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in
the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running
clock once symbol lock has been achieved, and is derived from the symbol clock. In Figure 8, MOCLK is shown in
with MOCLKINV = '1', the default state.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
Figure 8 - MPEG Output Data Waveforms
3.3.3 MPEG Output Timing
Maximum delay conditions: VDD = 3.0 V, CVDD = 1.62 V, Tamb = 70oC, Output load = 10 pF
Minimum delay conditions: VDD = 3.6 V, CVDD = 1.98 V, Tamb = 0oC, Output load = 10 pF
MOCLK frequency = 61.44 MHz.
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