MT352
Data Sheet
Value
Max.
450
Parameter
CLK clock frequency (Primary)
Symbol
fCLK
Unit
Min.
0
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Bus free time between a STOP and START condition
Hold time (repeated) START condition
LOW period of CLK clock
tBUFF
tHD;STA
tLOW
200
200
1300
600
200
100
100
HIGH period of CLK clock
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tR
Set-up time for a repeated START condition
Data hold time (when input)
Data set-up time
Rise time of both CLK and DATA signal.
Fall time of both CLK and DATA signals, (100 pF to ground)
Set-up time for a STOP condition
note 1
tF
20
tSU;STO
200
Table 2 - Timing of 2-Wire Bus
Note 1. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
3.3 MPEG
3.3.1 Data Output Header Format
Figure 7 - DVB Transport Packet Header Byte
15
Zarlink Semiconductor Inc.
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
