MT312 Functional Overview
ERROR
COUNT
VIT_ERRCNT[23:0]
0
0
VIT_ERRPER[23:0] DATA BITS
IRQ
Figure 5 - Viterbi error count measurement
Figure 5 shows the bit errors rising until the
maximum value programmed into the VIT
MAXERR[7:0] register and the dish alignment on the
satellite. This VIT MAXERR mode is enabled by
setting the FEC STAT EN register bit B0. Figure 5
above shows the bit errors rising to the maximum
value programmed and triggering a change of state
on the STATUS line.
maximum programmed value of VIT ERRPER[23:0]
is reached, when an interrupt is generated on the
IRQ line to advise the host microprocessor that a
new value of bit error count has been loaded into the
VIT ERRCNT [23:0] register. The IRQ line will go
high when the IE FEC register is read by the host
microprocessor. The error count may be expressed
as a ratio:
1.4.2 The Frame Alignment Block
VIT_ERRCNT[23:0]
---------------------------------------------------------
VIT_ERRPER[23:0]*4
The frame alignment algorithm detects a sequence
of correctly spaced synchronising bytes in the Viterbi
decoded bit-stream and arranges the input into
blocks of data bytes. Each block consists of 204
bytes for DVB and 147 bytes for DSS. In the DSS
mode, the synchronising byte is removed from the
data stream, so only 146 bytes of a block are passed
to the next stage. The frame alignment block also
removes the 180° phase ambiguity not removed by
Viterbi decoder.
1.4.1.2 Viterbi Error Count Coarse Indication
To assist in the process of aligning the receiver dish
aerial, a coarse indication of the number of bit errors
being received can be provided by monitoring the
STATUS line with the following set up conditions.
The frequency of the output waveform will be a
function of the bit error count (triggering the
VITERBI
COURSE
BIT
VIT_MAXERR[7:0]
ERROR
COUNT
0
0
DATA BITS
STATUS
Figure 6 - Viterbi error count coarse indication
12
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