MH89790B
Data sheet
4000 -is the number of frame alignment signals in a
one second interval.
The frame alignment and non-frame alignment signals for
timeslot zero are sourced by the control stream input
CSTi1 channel 16 and 17, respectively. The most
significant bit of timeslot zero will optionally contain the
cyclical redundancy check, CRC multiframe signal and Si
bits used for far-end CRC monitoring.
This formula provides a good approximation of the BER
given the following assumptions:
1. The bit errors are uniformly distributed on the line. In
other words, every bit in every channel is equally
likely to get an error.
Framing Algorithms
There are three distinct framers within the MH89790B.
These include a frame alignment signal framer, a
multiframe framer and a CRC framer. Figure 12 shows the
state diagram of the framing algorithms. The dotted lines
show optional features which are enabled in the
maintenance mode, that is selected by setting Maint bit of
the Master Control Word 3 to “1”.
2. The errors that occur in channel 0 are bit errors. If the
first assumption holds and the bit error rate is
reasonable, (below 10-3) then the probability of two or
more errors in 7 bits is very low.
Attenuation ROM
The frame synchronization circuit searches for the first
frame alignment signal within the bit stream. Once
detected, the frame counters are set to find the non-frame
alignment signal. If bit 2 of the non-frame alignment
signal is not one, a new search is initiated, else the framer
will monitor for the frame alignment in the next frame. If
the frame alignment signal is found, the device
immediately declares frame synchronization.
All transmit and receive data in the MH89790B is passed
through the digital attenuation ROM according to the
values set on bits 5 - 0 of data channels in the control
stream (CSTi0). Data can be attenuated on a per-channel
basis from 1 to 6 dB for both Tx and Rx data (refer Table
2).
Digital attenuation is applied on a per-channel basis to the
data found one channel after the control information
stored in the control channel CSTi0, i.e., control stream 0
channel 4 contains the attenuation setting for data stream
(DSTo) channel 5.
The multiframe synchronization algorithm is dependent
upon the state of frame alignment framer. The multiframe
framer will not initiate
a search for multiframe
synchronization until frame sync is achieved. Multiframe
synchronization will be declared on the first occurrence of
four consecutive zeros in the higher order quartet of
channel 16. Once multiframe synchronization is achieved,
the framer will only go out of synchronization after
detection of two errors in the multiframe signal or loss of
frame alignment synchronization.
Signalling Bit RAM
The A, B, C, & D Bit RAM is used to retain the status of
the per-channel signalling bits so that they may be
multiplexed into the Control Output Stream (CSTo). This
signalling information is only valid when the module is
The CRC synchronization algorithm is also dependent on
the state of the frame alignment framer, but is independent
of the multiframe synchronization. The CRC framer will
not initiate a search for CRC framing signal until frame
alignment synchronization is achieved. Once frame
alignment synchronization is acquired, the CRC framer
must find two framing signals in bit 1 of the non-frame
alignment signal. Upon detection of the second CRC
framing signal the MH89790B will immediately go into
CRC synchronization. When maintenance feature is
enabled (maint bit = 1) the CRC framer will force a
complete reframe of the device if CRC frame
synchronization is not found within 8 ms or more than
914 CRC errors occur per second.
synchronized to the received data stream.
If
synchronization is lost, the status of the signalling bits
will be retained for 6.0 ms provided the signalling
debounce is active.
Integrated into the signalling bit RAM is a debounce
circuit which will delay valid signalling bit changes for
6.0 to 8.0 ms. By debouncing the signalling bits, a bit
error in the latter will not affect the call in progress. (See
Table 3, bits 3-0 of channel 15 on the CSTi0 line.)
CEPT PCM 30 Format MUX
The internal multiplexer formats the data stream
corresponding to the CEPT PCM 30 format. The
multiplexer will use timeslots 1 to 15 and 17 to 31 for data
and timeslots 0 & 16 for the synchronization and channel
associated signalling.
Bipolar Line Receiver
The MH89790B receiver interfaces to the transmission
line through a pulse transformer which splits the received
AMI line signal into RxA and RxB. These two signals
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