Preliminary Information
Pin Description
No
1
2
3
4
MFR62340A-J
Description
Ground
Positive power supply
Positive power supply
Not Connected
Not Connected
Not Connected
Name
Gnd
V
CC
V
CC
RX_SD
1,4
Logic
Description
Ground
Positive power supply
Positive power supply
No
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Name
Gnd
V
CC
V
CC
Logic
NMOS
Receiver Signal Detect
channels 1 and 4
(channels 2 and 3 are not
monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40k
Ω
(note 1).
Receiver Signal Detect
channels 5 and 8
(Channels 6 and 7 are not
monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40k
Ω
(note 1).
Receiver Signal Detect
channels 9 and 12
(channels 10 and 11 are
not monitored).
High = Signal detected.
Low = No signal detected.
Open drain with internal
pull-up resistor 40k
Ω
(note 1).
Ground
Gnd
Do12c
Do12
Gnd
Do11c
Do11
Gnd
Do10c
Do10
Gnd
Do9c
Do9
Gnd
Do8c
Do8
Gnd
Do7c
Do7
Gnd
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
Ground
Data output No 12, inv.
Data output No 12.
Ground
Data output No 11, inv.
Data output No 11.
Ground
Data output No 10, inv.
Data output No 10.
Ground
Data output No 9, inv.
Data output No 9.
Ground
Data output No 8, inv.
Data output No 8.
Ground
Data output No 7, inv.
Data output No 7.
Ground
5
RX_SD
5,8
NMOS
6
RX_SD
9,12
NMOS
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Gnd
Do1
Do1c
Gnd
Do2
Do2c
Gnd
Do3
Do3c
Gnd
Do4
Do4c
Gnd
Do5
Do5c
Gnd
Do6
Do6c
Gnd
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
CML
Data output No 1.
Data output No 1, inv
Ground
Data output No 2.
Data output No 2, inv.
Ground
Data output No 3.
Data output No 3, inv.
Ground
Data output No 4.
Data output No 4, inv.
Ground
Data output No 5.
Data output No 5, inv.
Ground
Data output No 6.
Data output No 6, inv.
Ground
Note 1:
All RX_SD pins may be tied together (wired OR) to create one Receiver Signal Detect (RX_SD) output.
7
ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
