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    MAH28138NS 参数 Datasheet PDF下载

    MAH28138NS图片预览
    型号： MAH28138NS
    PDF下载： 下载PDF文件 查看货源
    内容描述： [Telecom IC,]
    分类和应用：
    文件页数/大小： 34 页 / 268 K
    品牌： ZARLINK [ ZARLINK SEMICONDUCTOR INC ]
     浏览型号MAH28138NS的Datasheet PDF文件第15页浏览型号MAH28138NS的Datasheet PDF文件第16页浏览型号MAH28138NS的Datasheet PDF文件第17页浏览型号MAH28138NS的Datasheet PDF文件第18页浏览型号MAH28138NS的Datasheet PDF文件第20页浏览型号MAH28138NS的Datasheet PDF文件第21页浏览型号MAH28138NS的Datasheet PDF文件第22页浏览型号MAH28138NS的Datasheet PDF文件第23页  
    F1:7glckafrnihp‘t-Tbus’O(B)mdoe  
    MA28138  
    The need for the RBI to perform a DMA operation is  
    indicated to the system’s DMA Arbiter by asserting the active  
    low DMARn output pin. When DMA operations are enabled,  
    permission to perform the DMA operation is indicated by the  
    arbiter using a low level on the RBl’s active low DMAKn input  
    pin. Once the DMA operation has been completed, DMARn is  
    de-asserted by the RBI; the arbiter responds by deasserting  
    DMAKn. DMAKn is interpreted by the RBI as permission to  
    drive the tri-state output busses; premature removal of DMAKn  
    will cause DMA transfer errors.  
    instigated) and an OSC edge (to which the generated pulse is  
    synchronised). The exact timing of the end of each DMARn  
    pulse is determined by the timing of DMAKn, but is also  
    synchronised to an OSC edge. Note that the DONE signal is  
    asserted in response to completion of the last DMA transfer.  
    The generation of all CPU signals is related to the OSC  
    clock. All signals which are generated on the CPU-side of the  
    MA28138 are intended to mimic those of an MAS281  
    microprocessor. In addition, provision has been made for two  
    extra control signals:  
    Figures 19 to 22 show 16 or 32 bit read or write DMA cycles  
    during each type of transfer (i.e. during II, IR, OR, IB and OB  
    mode transfers) where wait states do not need to be inserted  
    (i.e. where each machine cycle is completed in 5 OSC cycles).  
    Figure 23 shows a 16 bit DMA write cycle (II or IR mode  
    transfer) where 5 wait states need to be inserted.  
    • an active low DMA Data Direction signal (DMADDn),  
    intended to turn-around a bidirectional buffer between  
    the MA28138 and the system back-plane  
    • a system-level replacement for the SYNCn pulse  
    (SYNDn) which should be OR-ed with SYNCn.  
    The exact timing of the start of each DMARn pulse is  
    determined by two clock signals - an RIRCLK edge at a  
    specific point in the Interrogation (at which the DMA transfer is  
    Note that on MAS281 systems a bus time-out fault will  
    normally occur if the delay from DMARn↓ to DMAKn↓ exceeds  
    32µs.  
    21  
    Figure 19: ‘Input from I-bus’ (II) and ‘Input from R-bus’ (IR) mode DMA Controller 16 bit write cycle  
    (based on a 5 OSC machine cycle)  
    MA28138  
    DC CHARACTERISTICS AND RATINGS  
    Note: Stresses above those listed may cause permanent  
    damage to the device. This is a stress rating only and  
    functional operation of the device at these conditions, or at  
    any other condition above those indicated in the operations  
    section of this specification, is not implied. Exposure to  
    absolute maximum rating conditions for extended periods  
    may affect device reliability.  
    Parameter  
    Min  
    -0.5  
    -0.3  
    -20  
    -55  
    -65  
    Max  
    7
    Units  
    V
    Supply Voltage  
    Input Voltage  
    V
    DD+0.3  
    +20  
    125  
    150  
    V
    Current Through Any Pin  
    Operating Temperature  
    Storage Temperature  
    mA  
    °C  
    °C  
    Table 3: Absolute Maximum Ratings  
    Symbol  
    Parameter  
    Conditions  
    Min  
    Typ  
    Max  
    Units  
    VDD  
    VIHT  
    VILT  
    VIHC  
    VILC  
    VOH  
    VOL  
    IPDL  
    IPDH  
    IPUL  
    IPUH  
    IL  
    Supply Voltage  
    -
    4.5  
    2.0  
    5.0  
    5.5  
    VDD  
    0.8  
    VDD  
    0.2VDD  
    -
    V
    V
    TTL Input High Voltage  
    TTL Input Low Voltage  
    CMOS Input High Voltage  
    CMOS Input Low Voltage  
    Output High Voltage  
    Output Low Voltage  
    -
    -
    -
    VSS  
    0.8VDD  
    VSS  
    VDD-0.5  
    -
    -
    V
    -
    -
    V
    -
    -
    V
    IOH = -1mA  
    IOL = 4mA  
    -
    V
    -
    0.4  
    25  
    V
    Input Pull-down Current  
    Input Pull-down Current  
    Input Pull-up Current  
    VDD = 5.5V, VIN = VSS  
    VDD = 5.5V, VIN = VDD  
    VDD = 5.5V, VIN = VSS  
    VDD = 5.5V, VIN = VDD  
    VDD = 5.5V, VIN = VSS or VDD  
    VDD = 5.5V, VOUT = VSS  
    VDD = 5.5V, VOUT = VDD  
    VDD = 5.5V  
    -25  
    25  
    -
    µA  
    µA  
    µA  
    µA  
    µA  
    µA  
    µA  
    mA  
    mA  
    -
    400  
    -25  
    25  
    -400  
    -25  
    -10  
    -30  
    -30  
    -
    -
    Input Pull-up Current  
    -
    Input Leakage Current  
    Output Leakage Current  
    Output Leakage Current  
    Static Power Supply Current  
    Dynamic Power Supply Current  
    -
    10  
    IOZL  
    IOZH  
    IDD1  
    IDD2  
    -
    -
    30  
    30  
    0.02  
    6
    8
    f = 1MHz, VDD = 5.5V  
    -
    20  
    Notes: 1. VDD = 5V ±10% over full temperature range.  
    2. Total dose radiation not exceeding 105 Rads (Si).  
    3. Mil-Std-883, method 5005, subgroups 1, 2, 3.  
    4. All outputs are suitable for TTL/CMOS drive.  
    5. Electro-Static Discharge protection is provided for all pins.  
    6. Internal pull-up or pull-down resistors should not be relied upon for proper operation and/or  
    termination of input levels under all operating conditions without prior consultation with GPS.  
    7. Input and I/O leakage measurements are guaranteed but not tested at -55°C.  
    Table 4: DC Characteristics  
    27  
    MA28138  
    No.  
    Parameter  
    Min  
    Max  
    Units  
    T1  
    T2  
    T3  
    T4  
    T5  
    T6  
    T7  
    T8  
    T9  
    T10  
    RIRCLK ↓ to BCP (1:4), BCPVAL valid  
    RIRSYNC, RIRDATA, RIRVAL to RIRCLK ↑ (setup/hold)  
    RRRDATA, RRRVAL to RRRCLK ↑ (setup/hold)  
    RBRDATA, RBRVAL to RBRCLK ↑ (setup/hold)  
    RIRCLK ↓ to RRRINIT, RBRINIT valid  
    RIRCLK ↓ to RRTEN, RRTDATA valid (Normal response data)  
    RIRCLK ↓ to RRTEN, RRTDATA valid (Bit Polling response)  
    RIRCLK ↓ to RBTEN, RBTDATA valid  
    RIRCLK ↓ to UCC (0:6), UCCS valid  
    BIL (0:5), SREQ to RIRCLK ↑ (setup/hold)  
    Table 5: OBDH DBI Interface Characteristics (TBD)  
    No.  
    Parameter  
    Min  
    Max  
    Units  
    T11  
    T12  
    T13  
    T14  
    T15  
    RIRCLK ↓ to TFERR valid  
    RIRCLK ↓ to SYNCn ↑ (setup/hold)  
    RIRCLK ↓ to DONE ↓  
    DMARn ↑ to DONE ↑  
    RIRCLK ↓ to DONE ↑  
    Table 6: DMA Interface Characteristics (TBD)  
    No.  
    Parameter  
    Min  
    Max  
    Units  
    T16  
    T17  
    T18  
    T19  
    T20  
    T21  
    T22  
    T23  
    T24  
    T25  
    T26  
    T27  
    T28  
    T29  
    T30  
    T31  
    T32  
    T33  
    T34  
    T35  
    T36  
    SYNCn ↑ to DMARn ↓  
    DMAKn ↓ to AS, DSn, RDpWn, MpIOn, INpOPn valid and DMADDn ↑  
    DMAKn ↓ to Address valid  
    OSC ↑ to AS ↑  
    OSC ↓ to AS ↓  
    SYNCn ↑ to SYNDn ↑  
    OSC ↑ to DSn ↓  
    OSC ↑ to DMADDn ↓  
    OSC ↑ to AD High Impedance state  
    OSC ↑ to Data valid  
    OSC ↑ to SYNDn ↓  
    OSC ↓ to DSn ↑  
    DSn ↑ to Data (setup/hold)  
    OSC ↑ to DSn ↑  
    OSC ↑ to 2nd DMADDn ↑  
    OSC ↑ to 2nd 16 bit Address valid  
    OSC ↑ to DMARn ↑  
    DMAKn ↑ to DMADDn ↓  
    DMAKn ↑ to AS, DSn, RDpWn, MpIOn, INpOPn High Impedance state  
    DMAKn ↑ to AD High Impedance state  
    RDYn ↑ to OSC ↑ (setup/hold)  
    Notes: 1. VDD = 5V±1-% over full temperature range.  
    2. Total dose radiation not exceeding 105Rads(Si).  
    3. Tables 5, 6 and 7 contain Mil-Std-883, method 5005, subgroups 9, 10 and 11.  
    Table 7: Microprocessor Bus Interface Characteristics (TBD)  
    28  
    MA28138  
    Symbol Parameter  
    Conditions  
    Min.  
    Typ.  
    Max.  
    Units  
    CIN  
    COUT  
    Input Capacitance  
    Output Capacitance  
    VI = 0V  
    VI/O = 0V  
    -
    -
    3
    5
    5
    7
    pF  
    pF  
    NOTE 1: TA = 25˚C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured.  
    Table 8: Capacitance  
    Symbol  
    Parameter  
    Conditions  
    FT  
    Functionality  
    VDD = 4.5 - 5.5V, FREQ = 1 MHz  
    VIL = VSS, VIH = VDD, VOL = VOH = VDD/2  
    TEMP = -55˚C to +125˚C, GPS Pattern Set  
    Mil-Std-883 5005 subgroups 7, 8A, 8B  
    Table 9: Functionality  
    Subgroup  
    Definition  
    1
    Static characteristics specified in Table 4 at +25˚C  
    2
    Static characteristics specified in Table 4 at +125˚C  
    3
    Static characteristics specified in Table 4 at -55˚C  
    7
    Functional characteristics specified in Table 9 at +25˚C  
    Functional characteristics specified in Table 9 at +125˚C  
    Functional characteristics specified in Table 9 at -55˚C  
    Switching characteristics specified in Tables 5, 6 and 7 at +25˚C  
    Switching characteristics specified in Tables 5, 6 and 7 at +125˚C  
    Switching characteristics specified in Tables 5, 6 and 7 at -55˚C  
    8A  
    8B  
    9
    10  
    11  
    Table 10: Definition of Subgroups  
    29  
    MA28138  
    RBI PINLIST AND DESCRIPTIONS  
    Signal  
    Description  
    Pin  
    Type  
    VDD  
    VSS  
    +5 volt nominal power supply. Connect all pins  
    Power and signal ground. Connect all pins  
    55, 113  
    14, 47, 80  
    P/S  
    P/S  
    Power  
    MRSTn  
    Master reset active low  
    102  
    I (CS) (PD)  
    RESET  
    TA(0-5)  
    EXTFMT  
    EXTAEN  
    Terminal address to match I-bits 6-11 (table 1)  
    Extended format: when low TA0 = X  
    Enable use of Programmed Address and Broadcast Address  
    with ESA RBI-2 Command Set  
    37-42  
    43  
    44  
    I
    I
    I (PD)  
    POLL  
    GI(0-1)  
    PBP(0-4)  
    Poll group identifier to match I-bits 29-30  
    Poll bit position in 24 bit response  
    90-91  
    92-96  
    I
    I
    AD(0-15)  
    AS  
    µP address/data bus (5mA output)  
    Address strobe  
    21-36  
    56  
    I/O (TTL)  
    O
    DSn  
    Data strobe  
    57  
    O
    RDpWn  
    MPIOn  
    INpOPn  
    DMADDn  
    RDYn  
    SYNCn  
    OSC  
    SYNDn  
    Read when positive, write when negative  
    Memory when positive, I/O when negative  
    Instruction when positive, operand when negative  
    DMA data direction  
    Ready  
    Sync from µP  
    58  
    59  
    60  
    61  
    62  
    45  
    46  
    63  
    O
    O
    O
    O
    Processor  
    Bus  
    I (TTL) (PD)  
    I (TTL)  
    I (TTL)  
    O
    Oscillator from µP  
    RBI sync during DMA. OR with system sync  
    DMARn  
    DMAKn  
    DONE  
    DMA request  
    DMA acknowledge  
    DMA transfer correct and complete  
    DMA transfer error. RBI has aborted transfer  
    64  
    65  
    88  
    89  
    O
    I (TTL) (PU)  
    O
    O
    DMA  
    TFRERR  
    SREQ  
    User service request  
    66  
    I
    BIL(0-5)  
    UCC(0-6)  
    UCCS  
    User bi-level inputs  
    User control commands  
    UCC strobe when UCC value changes  
    67-72  
    73-79  
    87  
    I
    O
    O
    User  
    BCP(1-4)  
    BCPVAL  
    Broadcast pulses 1 to 4 (I-bits 3 to 6)  
    Broadcast pulses valid  
    97-100  
    101  
    O
    O
    Broadcast  
    RBTEN  
    RBI BT-bus transmitter enable  
    RBI BT-bus transmitter data  
    RBI BT-bus receiver initialisation  
    RBI BT-bus receiver validity  
    RBI BT-bus receiver data  
    RBI BT-bus receiver clock  
    RBI R-bus transmitter enable  
    RBI R-bus transmitter data  
    RBI R-bus receiver initialisation  
    RBI R-bus receiver validity  
    RBI R-bus receiver data  
    RBI R-bus receiver clock  
    RBI I-bus receiver validity  
    RBI I-bus receiver data  
    RBI I-bus receiver clock  
    RBI I-bus receiver sync  
    103  
    104  
    105  
    106  
    107  
    108  
    109  
    110  
    111  
    112  
    121  
    122  
    123  
    124  
    125  
    126  
    O
    O
    O
    I (PD)  
    I (PD)  
    I (PD)  
    O
    O
    O
    I (PD)  
    I (PD)  
    I (PD)  
    I (PD)  
    I (PD)  
    I (PD)  
    I (PD)  
    RBTDATA  
    RBRINIT  
    RBRVAL  
    RBRDATA  
    RBRCLK  
    RRTEN  
    RRTDATA  
    RRRINIT  
    RRRVAL  
    RRRDATA  
    RRRCLK  
    RIRVAL  
    OBDH  
    DBI  
    RIRDATA  
    RIRCLK  
    RIRSYNC  
    All other pins are used for test during manufacture and must be left unconnected.  
    Notes: 1. CS means CMOS Schmitt-trigger input.  
    2. TTL means TTL input levels.  
    3. Inputs not labelled use CMOS input levels.  
    4. PU means pull-up resistor.  
    5. PD means pull-down resistor.  
    6. Internal pull-up or pull-down resistors should not be relied upon for proper operation and/or  
    30  
    termination of input levels under all operating conditions without prior consulation with GPS.  
    MA28138  
    PACKAGE DIMENSIONS  
    Millimetres  
    Ref  
    Inches  
    Min.  
    Nom.  
    Max.  
    2.59  
    1.88  
    0.33  
    0.18  
    24.38  
    18.11  
    -
    Min.  
    Nom.  
    Max.  
    0.102  
    0.074  
    0.013  
    0.007  
    0.960  
    0.713  
    -
    A
    -
    -
    -
    -
    A1  
    1.37  
    -
    0.054  
    -
    b
    0.23  
    -
    0.009  
    -
    c
    0.10  
    -
    0.004  
    -
    D1, D2  
    -
    -
    -
    -
    E
    E2  
    e
    -
    -
    20.32  
    0.63  
    -
    -
    -
    -
    -
    -
    -
    0.800  
    0.025  
    -
    -
    -
    L
    6.35  
    7.11  
    0.250  
    0.280  
    XG533  
    Seating Plane  
    c
    A1  
    A
    E
    D1  
    Pin 1  
    117  
    17  
    L
    116  
    18  
    b
    E2  
    D2  
    TOP VIEW  
    132 Lead  
    e
    50  
    84  
    83  
    51  
    31  
    MA28138  
    RADIATION TOLERANCE  
    Total Dose (Function to specification)*  
    Transient Upset (Stored data loss)  
    Transient Upset (Survivability)  
    Neutron Hardness (Function to specification)  
    Single Event Upset**  
    1x105 Rad(Si)  
    5x1010 Rad(Si)/sec  
    >1x1012 Rad(Si)/sec  
    >1x1015 n/cm2  
    Total Dose Radiation Testing  
    For product procured to guaranteed total dose radiation  
    levels, each wafer lot will be approved when all sample  
    devices from each lot pass the total dose radiation test.  
    The sample devices will be subjected to the total dose  
    radiation level (Cobalt-60 Source), defined by the ordering  
    code, and must continue to meet the electrical parameters  
    specified in the data sheet. Electrical tests, pre and post  
    irradiation, will be read and recorded.  
    <1x10-10 Errors/bit day  
    Not possible  
    Latch Up  
    * Other total dose radiation levels available on request  
    ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit  
    GEC Plessey Semiconductors can provide radiation  
    testing compliant with Mil-Std-883 method 1019 Ionizing  
    Radiation (total dose) test.  
    Table 11: Radiation Hardness Parameters  
    ORDERING INFORMATION  
    Unique Circuit Designator  
    MAx28138xxxxx  
    Radiation Tolerance  
    S
    R
    Q
    H
    Radiation Hard Processing  
    100 kRads (Si) Guaranteed  
    300 kRads (Si) Guaranteed  
    1000 kRads (Si) Guaranteed  
    QA/QCI Process  
    (See Section 9 Part 4)  
    Test Process  
    (See Section 9 Part 3)  
    Package Type  
    F
    N
    Flatpack (Solder Seal)  
    Naked Die  
    Assembly Process  
    (See Section 9 Part 2)  
    Reliability Level  
    L
    Rel 0  
    C
    D
    E
    B
    S
    Rel 1  
    Rel 2  
    Rel 3/4/5/STACK  
    Class B  
    Class S  
    For details of reliability, QA/QC, test and assembly  
    options, see ‘Manufacturing Capability and Quality  
    Assurance Standards’ Section 9.  
    32  
    MA28138  
    SYNONYMS  
    ASIC  
    BC  
    BT-bus  
    CBR  
    CBT  
    CIT  
    CRR  
    CTU  
    DBI  
    Application Specific Integrated Circuit  
    (all ‘1’s) Broadcast Address  
    Block Transfer Bus  
    CTU mode, block transfer bus, receive  
    CTU mode, block transfer bus, transmit  
    CTU mode, interrogation unit, transmit  
    CTU mode, response bus, receive  
    Central terminal unit  
    MA28138  
    MA28139  
    µP  
    Remote bus interface (RBI) ASIC  
    OBDH bus terminal (OBT) ASIC  
    Microprocessor  
    Output to BT-bus  
    On board data handling  
    OBDH bus terminal (MA28139)  
    Output to R-bus  
    Programmable Address  
    OB  
    OBDH  
    OBT  
    OR  
    PA  
    PIU  
    Digital bus interface  
    Payload Interface Unit  
    DBU  
    DMA(C)  
    ESA  
    FET  
    FTC  
    GPS  
    IB  
    I-bus  
    ICU  
    II  
    Digital bus unit  
    R-bus  
    RBI  
    RBR  
    RBT  
    RIR  
    RRR  
    RRT  
    RT(U)  
    SBC  
    TA  
    Response bus  
    Direct Memory Access (Controller)  
    European Space Agency  
    Field effect transistor  
    Fault tolerant computer  
    GEC Plessey Semiconductors  
    Input from BT-bus  
    Interrogation bus  
    Intelligent control unit  
    Input from I-bus  
    Input from R-bus  
    Remote bus interface (MA28138)  
    RTU mode, block transfer bus, receive  
    RTU mode, block transfer bus, transmit  
    RTU mode, interrogation bus, receive  
    RTU mode, response bus, receive  
    RTU mode, response bus, transmit  
    Remote terminal (unit)  
    Single board computer  
    (hard-wired) Terminal Address  
    Very large scale integration  
    IR  
    VLSI  
    IUB  
    Internal user bus  
    HEADQUARTERS OPERATIONS  
    CUSTOMER SERVICE CENTRES  
    • FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45 Fax: (1) 64 46 06 07  
    • GERMANY Munich Tel: (089) 3609 06-0 Fax: (089) 3609 06-55  
    • ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993  
    GEC PLESSEY SEMICONDUCTORS  
    Cheney Manor, Swindon,  
    Wiltshire, SN2 2QW, United Kingdom.  
    Tel: (01793) 518000  
    • JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510  
    • NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 7023  
    • SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872  
    • SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36  
    • TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260  
    • UK, EIRE, DENMARK, FINLAND & NORWAY Swindon, UK  
    Tel: (01793) 518527/518566 Fax: (01793) 518582  
    Fax: (01793) 518411  
    GEC PLESSEY SEMICONDUCTORS  
    P.O. Box 660017,  
    1500 Green Hills Road, Scotts Valley,  
    California 95067-0017,  
    United States of America.  
    Tel: (408) 438 2900  
    Fax: (408) 438 5576  
    These are supported by Agents and Distributors in major countries world-wide.  
    © GEC Plessey Semiconductors 1995 Publication No. DS3591-4.4 March 1995  
    TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM.  
    This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to  
    be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or  
    service. The Company reserves the right to alter without prior knowledge the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide  
    only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of  
    any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose  
    failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.  

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