Le7920
Data Sheet
TEST CIRCUITS
A(TIP)
VTX
RL
2
SLIC
VAB
VL
RT
RRX
AGND
RL
2
RSN
B(RING)
I
L2-4 = 20 log (VTX / VAB
)
A. Two- to Four-Wire Insertion Loss
A(TIP)
VTX
SLIC
RT
RRX
VAB
RL
AGND
RSN
B(RING)
VRX
IL4-2 = 20 log (VAB / VRX
)
)
BRS = 20 log (VTX / VRX
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
1
A(TIP)
SLIC
VTX
<< RL
S1
ωC
RL
2
C
VL
RT
VAB
AGND
RL
VL
RRX
S2
2
RSN
B(RING)
VRX
S2 Open, S1 Closed
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
S2 Closed, S1 Open
4-L Long. Sig. Gen. = 20 log (VL / VRX
)
C. Longitudinal Balance
14
Zarlink Semiconductor Inc.